library ieee ;
use ieee.std_logic_1164.all;
-- use work.all; -- Proboca error

-- Definicion
entity cmp_reg1bit is
    port( data:  inout std_logic;
          rw:    in std_logic;
          e:     in std_logic;
          clock: in std_logic );
end cmp_reg1bit;

-- Arquitectura
architecture behv of cmp_reg1bit is

    component cmp_not
        port( D_in:  in std_logic;
              D_out: out std_logic );
    end component;

    component cmp_and
    port( A: in std_logic;
          B: in std_logic;
          F: out std_logic );
    end component;

    component cmp_ts
    port( D_in: in std_logic;
    	  E: in std_logic;
          D_out: out std_logic );
    end component;

    component cmp_dff
    port( data_in: in std_logic;
          clock: in std_logic;
          data_out: inout std_logic );
    end component;

    signal nrw: std_logic;
    signal dff: std_logic; 
    signal qff: std_logic;
    signal cs: std_logic;
    signal ce: std_logic;
    signal clocko: std_logic;
begin
    and_0: cmp_and port map (rw, e, ce);
    not_0: cmp_not port map (rw, nrw);
    and_1: cmp_and port map (nrw, e, cs);
    and_10: cmp_and port map (clock, ce, clocko);
    -- and_2: cmp_and port map (controlEntrada, clock, controlEntrada1);
    -- and_3: cmp_and port map (controlSalida, clock, controlSalida1);
    ts_1: cmp_ts port map (data, ce, dff);
    dff_0: cmp_dff port map (dff, clocko, qff);
    ts_0: cmp_ts port map (qff, cs, data);
end behv;

